Electronic information handling or computerized systems, whether large machines, microcomputers or small handheld devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices.
Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells. Data and status information of the memory device are provided to external devices through a set of DQ or data signal lines.
One particular form of semiconductor memory device is a non-volatile memory referred to as flash memory. Flash memory includes an array of memory cells made up of floating-gate transistors. A charge stored on the floating gate of the transistor determines the threshold voltage of the transistor. Various sensing methods can be used to detect the threshold voltage and thus determine the data value associated with an individual memory cell.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. Specialized portable devices are consuming large quantities of flash memory and are continually pushing for lower voltages and higher densities to decrease power requirements, reduce size and increase functionality. Such portable devices include digital cellular or other wireless communication applications, digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment.
In system applications requiring integration of logic devices and memory devices, three approaches are known. A first approach is to combine the logic device and the memory device in a single application-specific integrated circuit (ASIC) chip using a low-cost memory process. Such an approach is a low-cost alternative, but memory processes lack the metal layers and circuit complexity necessary to produce a high-performance logic device. Thus, such an ASIC provides relatively limited performance of the logic core.
A second approach is to combine the logic device and the memory device in a single-chip ASIC chip using a more sophisticated logic process providing for more metal layers and masks. While more expensive than the first approach, the logic process supports high-performance logic cores. In either of these approaches, the flexibility of the ASIC is limited as the functionality of the logic core and the size of the memory device are fixed. Modifications in response to market demands or new technologies generally require extensive retooling whether the modification affects only the memory portion or the logic portion of the ASIC. In addition, for related systems differing only in the amount of memory provided, separate ASICs would be required for each system.
FIG. 1A is a simplified block diagram of an electronic system 100 produced as a single-chip ASIC and coupled to a system bus 150. The electronic system 100 generally includes a memory core block 110 containing the memory cells and sensing circuitry; a control, logic and interconnect block 112; an analog block 114 providing the various internal voltage potentials from the supply potential; a logic core block 116; a static random access memory (SRAM) block 118 for caching data between the logic core block 116 and the memory core block 110; an input/output (I/O) block 120 for interfacing with the system bus 150; and often a customer-specific block 122 containing customer-specific functionality for the ASIC. It is noted that FIG. 1A is an abstraction of an electronic system and that the physical location and relative sizing of the individual blocks in the figure are not necessarily representative of an actual electronic system.
To provide more flexibility, albeit at increased cost, size and power requirements, a third approach to integrating a logic device and a memory device uses a separate logic device and a separate memory device. In this manner, the memory device and the logic device each can be produced using a process optimized for the particular device. Furthermore, responding to changing markets or new technology is relatively easy, in that only the relevant portion need be altered. In addition, related systems differing only in the amount of memory provided may be produced simply by substituting the appropriate memory device.
FIG. 1B is a simplified block diagram of an electronic system 100 having a memory device 102 and a logic device 104 each coupled to a system bus 150. The memory device 102 generally includes a memory core block 110 containing the memory cells and sensing circuitry; a control, logic and interconnect block 112; an analog block 114 providing the various internal voltage potentials from the supply potential; and an I/O block 124 for interfacing with the system bus 150. The logic device 104 generally includes a logic core block 116; a static random access memory (SRAM) block 118 for caching data between the logic core block 116 and the memory core block 110 of the memory device 102; an input/output (I/O) block 120 for interfacing with the system bus 150; and often a customer-specific block 122 containing customer-specific functionality for the logic device 104. An electronic system of the type shown in FIG. 1B may require 5–10% additional semiconductor real estate over an equivalent system of the type shown in FIG. 1A, due to the redundancy of the I/O circuitry. It is noted that FIG. 1B is an abstraction of an electronic system and that the physical location and relative sizing of the individual blocks or semiconductor chips in the figure are not necessarily representative of an actual electronic system.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for the integration of memory devices and logic devices supporting system flexibility, lower power requirements and reduced size.